Field of the Invention
The invention relates to a circuit configuration for converting logic signal levels from an input signal to an output signal. In addition, the invention relates to a use of such a circuit configuration in a semiconductor memory.
Such signal level converters are often used in electronic circuits in order to level-convert logic signal levels from a circuit region supplied by a first supply voltage and to forward them to a circuit region supplied by another supply voltage. One application of such circuits is in dynamic random access memories (DRAMs), where the circuit regions within the semiconductor memory and, in comparison therewith, the circuit regions disposed directly on the output side are supplied by different supply voltage bus bars. The supply voltage for the inner circuit regions is usually lower than that for the outer circuit regions.
A fundamental requirement made of such a signal level converter is that the signal is as far as possible not delayed and a high operating frequency can be complied with and, moreover, that the signal characteristics in particular the steepness of rising and falling edges, are as far as possible not changed. In this case, it is also the intention that the duty ratio of the logic signal to be converted, that is to say the ratio between high and low phases of the signal, is as far as possible not changed during the conversion.
A conventional level converter embodied in present-day customary CMOS circuit technology has two cross-coupled current paths with series-connected p-channel and n-channel field-effect transistors. Since the signal level swing differs at the input and at the output, by way of example the high level being present at the positive pole of the inner supply voltage on the input side and at the positive pole of the outer supply voltage on the output side, it has proved to be favorable to confer different dimensioning on the driver capability of the n-channel and p-channel field-effect transistors of a current path in such a level converter. In this case, the n-channel field-effect transistor, connected to a reference-ground potential or ground, is to be provided with a higher current driver capability than the p-channel field-effect transistor, connected to the positive supply potential. What is thereby achieved is that, even in the event of different operating conditions, the level converter switches sufficiently reliably and does not, for instance, remain in a floating state.
The different dimensioning of p-channel and n-channel field-effect transistors in the conventional level converter has the disadvantage that a rising edge and a falling edge of a logic signal to be converted are converted differently. The gradient of a rising edge is shallower than the gradient of a falling edge. As a result, the duty ratio of a signal to be converted is changed by the conventional level converter during the signal conversion. This effect could be compensated for by compensatory circuit measures, so that the digital signal is still identified sufficiently reliably by downstream circuits.
What is problematic, however, is that, as is known, the parameters of transistors in integrated circuits are subject to not inconsiderable fluctuations. The aforementioned effect of distortion of the duty ratio may thus be subject to corresponding fluctuations between different integrated semiconductor modules, so that the functionality of the integrated circuit is jeopardized in the unfavorable case. In order to provide a remedy, additional transistors that can optionally be connected in after production and testing have been necessary hitherto in order to provide for compensation. This necessitates additional outlay in the production and testing of the semiconductor circuit.
It is accordingly an object of the invention to provide a circuit configuration for converting logic signal levels that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has a reliable circuit behavior and requires less outlay in its production.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for converting logic signal levels. The circuit configuration contains an input terminal for receiving an input signal to be converted, and level converters, including a first level converter and a second level converter each having an input receiving the input signal in a complementarily fashion with respect to each other. Each of the level converters further contains an output, and two current paths, including a first current path and a second current path. The current paths each have two series-connected transistors of complementary conductivity types and the transistors have control terminals. The transistors of the same conductivity type of different ones of the current paths being controlled complementarily with respect to one another and the transistors of a respective same one of the current paths being controlled complementarily with respect to one another. A logic combination element has an output and inputs coupled to the output of each of the level converters. A togglable storage element has an output and an input connected to the output of the logic combination element. An output terminal is connected to the output of the togglable storage element.
Such a circuit configuration is used in a read data signal path of a semiconductor memory module for converting a data signal read from a memory cell to an output driver, which is connected to a terminal for providing a data signal outside the semiconductor memory.
The circuit configuration according to the invention provides two level converters whose output signals are combined with one another in order subsequently to drive a togglable storage element. From a functional standpoint, the level converters only provide the information that an edge of the input signal has occurred. The temporal succession of the information about the occurrence of an edge is forwarded to the togglable storage element and used there again for forming the output signal. The edge steepness of a rising or falling edge is determined by the dimensioning of the components in the togglable storage element on the output side. Since the converted signal levels are already present there and all the circuit sections and signal levels are already present at the level of the outer supply voltage on the output side or of the signal level swing on the output side, it is possible to use conventional inverters. These inverters are dimensioned as usual such that they generate rising and falling edges with rise and fall rates, respectively, that are identical in magnitude. What is thereby achieved overall is that the converted logic signal, on the output side, again has the duty ratio corresponding to the input signal.
In the circuit configuration according to the invention, all the circuit elements connected upstream of the two level converters are supplied by the lower inner supply voltage of the level converter. All the functional elements connected downstream of the level converters are supplied by the higher output-side supply voltage of the level converter. Thus, a respective inverter is additionally provided between the outputs of the level converters and the input of the logic combination element, the inverter being supplied by the output-side supply voltage.
The level converters have current paths with field-effect transistors of complementary channel types that are connected in series with respect to their drain-source paths. The transistors of a current path and transistors of the same channel type of different current paths are controlled complementarily with respect to one another.
These current paths are supplied by the output-side supply voltage. An inverter connected between the n-channel field-effect transistors of the different current paths, the transistors being connected to reference-ground potential, is still supplied by the input-side supply voltage. The inverter is connected between the gate terminals of the n-channel field-effect transistors.
The logic combination element is expediently a NAND gate. The NAND gate generates a low level on the output side only if two high levels are fed to it on the input side. This is the case in the circuit configuration when one of the level converters has already converted a falling edge while the rising edge, on account of the lower rise rate, has not yet risen to a sufficiently high signal level that the switching threshold value of the subsequent circuits has been reached. The information about the duty ratio of the signal to be converted is now present in the falling edge of the signal at the output of the NAND gate. The togglable storage element connected downstream is switched with the falling edge and generates rising and falling edges of the output signal alternately in succession.
In accordance with an added feature of the invention, a second inverter has an input connected to the input terminal and an output connected to the input of the first level converter. A transfer gate is provided and has an input connected to the input terminal and an output connected to the input of the second level converter.
In accordance with an additional feature of the invention, third inverters are provided and each has an input and an output. In each of the level converters, one set of the transistors being two transistors of the same conductivity type includes a first transistor connected to the input of a respective third inverter and a second transistor connected to the output of the respective third inverter, such that the control terminals of the first and second transistors are connected to each other through the respective third inverter.
In accordance with another feature of the invention, the second inverter and the third inverters of the level converters have supply voltage terminals for receiving a first supply voltage. The current paths, the logic combination element, the toggable storage element, and the first inverters in each case have terminals for receiving a second supply voltage. The second supply voltage is higher than the first supply voltage.
In accordance with a concomitant feature of the invention, in each of the level converters, each of the current paths has an n-channel field-effect transistor with a source-drain path and a gate terminal and a p-channel field-effect transistor with a gate terminal and a drain-source path connected in series with the source-drain path of the n-channel field-effect transistor at a coupling node. The gate terminal of the n-channel field-effect transistor of the first current path is coupled to the input terminal. Each of the level converters has an inverter with an input connected to the gate terminal of the n-channel field-effect transistor of the first current path and an output connected to the gate terminal of the n-channel field-effect transistor of the second current path. In each of the level converters, the coupling node of the transistors of the first current path is connected to the gate terminal of the p-channel field-effect transistor of the second current path and to the output of the level converter. In each of the level converters, the coupling node of the transistors of the second current path is connected to the gate terminal of the p-channel transistor of the first current path.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for converting logic signal levels, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.